A Modular Digital VLSI Flow for High-productivity SoC Design
Brucek Khailany,
Evgeni Krimer,
Rangharajan Venkatesan,
Jason Clemons,
Joel S. Emer,
Matthew Fojtik,
Alicia Klinefelter,
Michael Pellauer,
Nathaniel Pinckney,
Yakun Sophia Shao,
Shreesha Srinath,
Christopher Torng,
Sam (Likun) Xi,
Yanqing Zhang,
Brian Zimmer
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Abstract
A high-productivity digital VLSI flow for designing complex SoCs is presented. The flow includes high-level synthesis tools, an object-oriented library of synthesizable SystemC/C++ components, and a modular VLSI physical design approach based on fine-grained globally asynchronous locally synchronous (GALS) clocking. The flow was demonstrated on a 16nm FinFET testchip targeting machine learning and computer vision.