This paper presents iRazor, a lightweight error detection and correction approach, to suppress the cycle time margin that is traditionally added to very large scale integration systems to tolerate process, voltage, and temperature variations. iRazor …
In recent years, operating at near-threshold supply voltages has been proposed to improve energy efficiency in circuits, yet decreased efficacy of dynamic voltage scaling has been observed in recent planar technologies. However, foundries have …
It is well known that technology scaling has led to increasing process/voltage/temperature/aging margins that substantially degrade performance and power in modern processors and SoCs. One approach to address these large timing margins is the use of …
A switched-capacitor voltage regulator (SCVR) that dithers flying capacitance (C$_textrmFLY$) to reduce output ripple is presented. The proposed technique is implemented in a 40-phase SCVR with 4b C$_textrmFLY$ modulation in 65nm CMOS. At 2.3V input, …
We propose Bubble Razor, an architecturally independent approach to timing error detection and correction that avoids hold-time issues and enables large timing speculation windows. A local stalling technique that can be automatically inserted into …
Several methods that eliminate timing margins by detecting and correcting transient delay errors have been proposed. These Razor-style systems replace critical flip-flops with ones that detect late arriving signals, and use architectural replay to …