Several methods that eliminate timing margins by detecting and correcting transient delay errors have been proposed. These Razor-style systems replace critical flip-flops with ones that detect late arriving signals, and use architectural replay to correct errors. However, none of these methods have been applied to a complete commercial processor due to their architectural invasiveness. In addition, these Razor techniques introduce significant hold time constraints that are difficult to meet given worsening timing variability. To address these two issues we propose Bubble Razor (B-Razor), which uses a novel error-detection technique based on two-phase latch timing and a local replay mechanism that can be inserted automatically in any design. The error detec tion technique breaks the dependency between minimum delay and speculation window, restoring hold-time constraints to conventional values and allowing timing speculation of up to 100% of nominal delay. The large timing specula tion makes Bubble Razor especially applicable to low-voltage designs where tim ing variation grows exponentially.