Bubble Razor: Eliminating Timing Margins in an ARM Cortex-M3 Processor in 45 nm CMOS Using Architecturally Independent Error Detection and Correction

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Abstract

We propose Bubble Razor, an architecturally independent approach to timing error detection and correction that avoids hold-time issues and enables large timing speculation windows. A local stalling technique that can be automatically inserted into any design allows the system to scale to larger processors. We implemented Bubble Razor on an ARM Cortex-M3 microprocessor in 45 nm CMOS without detailed knowledge of its internal architecture to demonstrate the technique’s automated capability. The flip-flop based design was converted to two-phase latch timing using commercial retiming tools; Bubble Razor was then inserted using automatic scripts. This system marks the first published implementation of a Razor-style scheme on a complete, commercial processor. It provides an energy efficiency improvement of 60% or a throughput gain of up to 100% compared to operating with worst case timing margins.

Type
Journal article
Publication
IEEE Journal of Solid-State Circuits
Date
Adaptive circuits architecturally-independent error detection-correction ARM Cortex-M3 microprocessor automatic scripts bubble razor Clocks CMOS CMOS logic circuits Delay dynamic voltage and frequency scaling (DVFS) efficiency 60 percent energy efficiency improvement error correction Error correction flip-flop-based design flip-flops Latches local stalling technique logic design microprocessor chips Pipeline processing Random access memory size 45 nm time borrowing timing error correction timing error detection timing margin elimination timing speculation timing speculation windows two-phase latch timing two-phase latches variation tolerance