A reconfigurable sense amplifier with auto-zero calibration and pre-amplification in 28nm CMOS


This work presents an area-efficient and variation-tolerant small-signal differential sensing (VTS) scheme that modifies the conventional SA circuit to include: 1) a structure for on-the-fly, auto-zeroing offset compensation, 2) pre-amplification of bitline differential by reconfiguring the SA inverter pair as amplifiers, and 3) latching of the amplified voltage differential by returning the SA to its conventional cross-coupled configuration. The approach is demonstrated to improve SA robustness over conventional sensing at isosensing time without area overhead (Fig. 13.7.1). Conversely, sensing time can be reduced at iso-robustness and area. Measurements of a 28nm CMOS test chip show that an iso-area VTS scheme improves offset noise tolerance by -1.2σVth or sensing speed by up to 42% at iso-robustness (textless;0.3% failure rate).

2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)