This paper describes a parallelized radix-4 scalable Montgomery multiplier implementation. The design does not require hardware multipliers, and uses parallelized multiplication to shorten the crit- ical path. By left-shifting the sources rather than right-shifting the result, the latency between pro- cessing elements is shortened from two cycles to nearly one. Multiplexers are used to select pre- computed products. Carry-save adders propagate carry bits before words are discarded. The new design can perform 1024-bit modular exponentiation in 9.4 ms and 256-bit exponentiation in 0.38 ms using 4997 Virtex2 4-input lookup tables, while consuming 30% fewer LUTs than a previous par- allelized radix-4 design. This is comparable to radix-2 for long multiplies and nearly twice as fast for short ones.